89 lines
3.9 KiB
INI
89 lines
3.9 KiB
INI
source [find interface/jlink.cfg]
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adapter driver jlink
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transport select swd
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set CHIPNAME stm32h750vbt6
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# enable stmqspi
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if {![info exists QUADSPI]} {
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set QUADSPI 1
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}
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source [find target/stm32h7x.cfg]
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proc qspi_init { } {
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global a
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mmw 0x580244E0 0x000007FF 0 ;# RCC_AHB4ENR |= GPIOAEN-GPIOKEN (enable clocks)
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mmw 0x580244D4 0x00004000 0 ;# RCC_AHB3ENR |= QSPIEN (enable clock)
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sleep 1 ;# Wait for clock startup
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# PF10:AF09:H, PF09:AF10:H, PF08:AF10:H, PF07:AF09:H, PF06:AF09:H, PG06:AF10:H
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# Port F: PF10:AF09:H, PF09:AF10:H, PF08:AF10:H, PF07:AF09:H, PF06:AF09:H
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mmw 0x58021400 0x002AA000 0x00155000 ;# MODER
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mmw 0x58021408 0x002AA000 0x00155000 ;# OSPEEDR
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mmw 0x5802140C 0x00000000 0x003FF000 ;# PUPDR
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mmw 0x58021420 0x99000000 0x66000000 ;# AFRL
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mmw 0x58021424 0x000009AA 0x00000655 ;# AFRH
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# Port G: PG06:AF10:H
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mmw 0x58021800 0x00002000 0x00001000 ;# MODER
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mmw 0x58021808 0x00002000 0x00001000 ;# OSPEEDR
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mmw 0x5802180C 0x00000000 0x00003000 ;# PUPDR
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mmw 0x58021820 0x0A000000 0x05000000 ;# AFRL
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# correct FSIZE is 0x16, however, this causes trouble when
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# reading the last bytes at end of bank in *memory mapped* mode
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# for single flash mode w25q64jv
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;# 010101010000000000000 0 011000
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mww 0x52005000 0x05500018 ;# QUADSPI_CR: PRESCALER=5, APMS=1, FTHRES=1, FSEL=0, DFM=0, SSHIFT=1, TCEN=1
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mww 0x52005004 0x00160500 ;# QUADSPI_DCR: FSIZE=0x16, CSHT=0x05, CKMODE=0
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;# FSIZE flash的大小。
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mww 0x52005030 0x00001000 ;# QUADSPI_LPTR: deactivate CS after 4096 clocks when FIFO is full
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;# 11010000000000 10 010100000011
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mww 0x52005014 0x0D002503 ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x1, DCYC=0x0, ADSIZE=0x2, ADMODE=0x1, IMODE=0x1
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mmw 0x52005000 0x00000001 0 ;# QUADSPI_CR: EN=1
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# Exit QPI mode
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#mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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#mww 0x52005014 0x000003F5 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x3, INSTR=Exit QPI
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sleep 1
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# reset flash
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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mww 0x52005014 0x00000166 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=0x66
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mww 0x52005014 0x00000199 ;# QUADSPI_CCR: FMODE=0x0, DMODE=0x0, DCYC=0x0, ADSIZE=0x0, ADMODE=0x0, IMODE=0x1, INSTR=0x99
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# memory-mapped read mode with 3-byte addresses
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mmw 0x52005000 0x00000002 0 ;# QUADSPI_CR: ABORT=1
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;# 11 11 0 00100 00 11 10 11 01 11101011
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mww 0x52005014 0x0F10EDEB ;# QUADSPI_CCR: FMODE=0x3, DMODE=0x3, DCYC=0x4, ADSIZE=0x2, ADMODE=0x3, IMODE=0x1, INSTR=READ
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;mww 0x52005014 0x0D002503
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}
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$_CHIPNAME.cpu0 configure -event reset-init {
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global QUADSPI
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mmw 0x52002000 0x00000004 0x0000000B ;# FLASH_ACR: 4 WS for 192 MHZ HCLK
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mmw 0x58024400 0x00000001 0x00000018 ;# RCC_CR: HSIDIV=1, HSI on
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mmw 0x58024410 0x10000000 0xEE000007 ;# RCC_CFGR: MCO2=system, MCO2PRE=8, HSI as system clock
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mww 0x58024418 0x00000040 ;# RCC_D1CFGR: D1CPRE=1, D1PPRE=2, HPRE=1
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mww 0x5802441C 0x00000440 ;# RCC_D2CFGR: D2PPRE2=2, D2PPRE1=2
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mww 0x58024420 0x00000040 ;# RCC_D3CFGR: D3PPRE=2
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mww 0x58024428 0x00000040 ;# RCC_PPLCKSELR: DIVM3=0, DIVM2=0, DIVM1=4, PLLSRC=HSI
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mmw 0x5802442C 0x0001000C 0x00000002 ;# RCC_PLLCFGR: PLL1RGE=8MHz to 16MHz, PLL1VCOSEL=wide
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mww 0x58024430 0x01070217 ;# RCC_PLL1DIVR: 192 MHz: DIVR1=2, DIVQ=8, DIVP1=2, DIVN1=24
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mmw 0x58024400 0x01000000 0 ;# RCC_CR: PLL1ON=1
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sleep 1
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mmw 0x58024410 0x00000003 0 ;# RCC_CFGR: PLL1 as system clock
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sleep 1
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adapter speed 24000
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if { $QUADSPI } {
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qspi_init
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}
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} |