213 lines
4.6 KiB
Plaintext
213 lines
4.6 KiB
Plaintext
/* STM32H750XBHx - RT-Thread linker script (GCC/ld)
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*
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* XIP QSPI FLASH: 0x9000_0000 (8MB) -> .isr_vector/.text/.rodata/const tables
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* DTCM RAM : 0x2000_0000 (128KB)-> .data/.bss (fast CPU access, NOT for DMA)
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* AXI SRAM : 0x2400_0000 (512KB)-> system heap recommended
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* D2 SRAM : 0x3000_0000 (288KB)-> USB DMA buffers (nocache/buffer) recommended
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* D3 SRAM : 0x3800_0000 (64KB)
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* ITCM RAM : 0x0000_0000 (64KB)
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*/
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ENTRY(Reset_Handler)
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/* Memory regions */
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MEMORY
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{
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ITCMRAM (xrw) : ORIGIN = 0x00000000, LENGTH = 64K
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DTCMRAM (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
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RAM (xrw) : ORIGIN = 0x24000000, LENGTH = 512K
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RAM_D2 (xrw) : ORIGIN = 0x30000000, LENGTH = 288K
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RAM_D3 (xrw) : ORIGIN = 0x38000000, LENGTH = 64K
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FLASH (rx) : ORIGIN = 0x90000000, LENGTH = 8192K
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}
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/* MSP stack top (startup uses this) */
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_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM);
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/* Only for link-check / startup template compatibility
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* NOTE: RT-Thread thread stacks are NOT defined by this.
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*/
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_Min_Stack_Size = 0x800;
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_Min_Heap_Size = 0x400;
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/* RT-Thread heap range in AXI SRAM (use these in board.c/board.h) */
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PROVIDE(__heap_start__ = ORIGIN(RAM));
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PROVIDE(__heap_end__ = ORIGIN(RAM) + LENGTH(RAM));
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SECTIONS
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{
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/* Vector table */
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.isr_vector :
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{
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. = ALIGN(4);
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KEEP(*(.isr_vector))
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. = ALIGN(4);
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} > FLASH
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/* Code + rodata + RT-Thread tables */
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.text :
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{
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. = ALIGN(4);
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_stext = .;
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*(.text)
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*(.text*)
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*(.glue_7)
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*(.glue_7t)
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*(.eh_frame)
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*(.rodata)
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*(.rodata*)
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/* finsh shell symbol table */
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. = ALIGN(4);
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__fsymtab_start = .;
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KEEP(*(FSymTab))
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__fsymtab_end = .;
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. = ALIGN(4);
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__vsymtab_start = .;
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KEEP(*(VSymTab))
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__vsymtab_end = .;
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/* rt_init section */
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. = ALIGN(4);
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__rt_init_start = .;
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KEEP(*(SORT(.rti_fn*)))
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__rt_init_end = .;
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/* optional old-style ctors/dtors (some libs still emit these) */
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. = ALIGN(4);
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PROVIDE(__ctors_start__ = .);
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KEEP(*(SORT(.ctors.*)))
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KEEP(*(.ctors))
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PROVIDE(__ctors_end__ = .);
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. = ALIGN(4);
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PROVIDE(__dtors_start__ = .);
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KEEP(*(SORT(.dtors.*)))
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KEEP(*(.dtors))
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PROVIDE(__dtors_end__ = .);
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. = ALIGN(4);
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_etext = .;
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} > FLASH
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/* ARM exception tables */
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.ARM.extab :
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{
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. = ALIGN(4);
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*(.ARM.extab* .gnu.linkonce.armextab.*)
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. = ALIGN(4);
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} > FLASH
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.ARM.exidx :
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{
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. = ALIGN(4);
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__exidx_start = .;
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*(.ARM.exidx* .gnu.linkonce.armexidx.*)
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__exidx_end = .;
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. = ALIGN(4);
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} > FLASH
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/* C++ init arrays */
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.preinit_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN(__preinit_array_start = .);
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KEEP(*(.preinit_array*))
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PROVIDE_HIDDEN(__preinit_array_end = .);
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. = ALIGN(4);
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} > FLASH
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.init_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN(__init_array_start = .);
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KEEP(*(SORT(.init_array.*)))
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KEEP(*(.init_array*))
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PROVIDE_HIDDEN(__init_array_end = .);
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. = ALIGN(4);
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} > FLASH
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.fini_array :
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{
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. = ALIGN(4);
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PROVIDE_HIDDEN(__fini_array_start = .);
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KEEP(*(SORT(.fini_array.*)))
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KEEP(*(.fini_array*))
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PROVIDE_HIDDEN(__fini_array_end = .);
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. = ALIGN(4);
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} > FLASH
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/* Initialized data -> DTCM, load from FLASH */
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.data :
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{
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. = ALIGN(4);
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_sdata = .;
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*(.data)
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*(.data*)
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*(.RamFunc)
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*(.RamFunc*)
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. = ALIGN(4);
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_edata = .;
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} > DTCMRAM AT> FLASH
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/* Used by startup to copy .data from FLASH to DTCM */
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_sidata = LOADADDR(.data);
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/* BSS -> DTCM */
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.bss (NOLOAD) :
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{
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. = ALIGN(4);
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_sbss = .;
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__bss_start__ = _sbss;
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*(.bss)
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*(.bss*)
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*(COMMON)
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. = ALIGN(4);
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_ebss = .;
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__bss_end__ = _ebss;
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PROVIDE(__bss_end = .);
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} > DTCMRAM
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/* ---------------- USB DMA buffers in D2 SRAM ----------------
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* Put all USB DMA related buffers here:
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* __attribute__((section(".usb_nocache"))) / ".noncacheable"
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* Align to 32 bytes for safety (future D-Cache + cache-line ops)
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*/
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.usb_nocache (NOLOAD) :
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{
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. = ALIGN(32);
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__usb_nocache_start__ = .;
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*(.usb_nocache)
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*(.usb_nocache*)
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*(.noncacheable)
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*(.noncacheable*)
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. = ALIGN(32);
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__usb_nocache_end__ = .;
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} > RAM_D2
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/* End symbols (end of DTCM used sections) */
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PROVIDE(end = .);
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PROVIDE(_end = .);
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/* Link check: ensure DTCM has room for at least Min Stack */
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._user_stack (NOLOAD) :
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{
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. = ALIGN(8);
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. = . + _Min_Stack_Size;
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. = ALIGN(8);
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} > DTCMRAM
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}
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/* Optional: sanity checks */
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ASSERT(_ebss <= (ORIGIN(DTCMRAM) + LENGTH(DTCMRAM)), "DTCMRAM overflow: .data/.bss too large");
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ASSERT(__usb_nocache_end__ <= (ORIGIN(RAM_D2) + LENGTH(RAM_D2)), "D2 overflow: USB nocache section too large");
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